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* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4753B LSI Universal timer module
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Universal timer module
DESCRIPTION The HEF4753B is a universal timer module for counting and dividing as well as for event-recognition and manipulation of input sequences. The following functions are included: synchronization and edge-detection of the input signal, programmable counter, clock divider with different lengths, operating mode decoder, control logic and output multiplexer. Depending on the operating mode and the application, the circuit works as a presettable 8-bit counter with
HEF4753B LSI
transient-pulse suppression, pulse duration selector divider, counter, positive or negative edge delaying module or low-frequency control circuit. All manipulation possibilities depend on a time scaling, which is adjustable by the 8-bit programmable counter and the system clock. The system clock can be divided internally by 1, 16, 256 or 4096 as input clock for the counter. In all cases the manipulated input sequence appears at the only output OUT.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category LSI See Family Specifications
January 1995
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Philips Semiconductors
Product specification
Universal timer module
FUNCTION TABLES INPUTS
HEF4753B LSI
OPERATING MODE LFC L L H H H L Fig.2 Pinning diagram. LFC Notes 1. H = HIGH state (the more positive voltage). 2. L = LOW state (the less positive voltage). HEF4753BP(N): HEF4753BD(N): 18-lead DIL; plastic (SOT102-3) 18-lead DIL; ceramic (cerdip) (SOT133) ( ): Package Designator North America Y L H H L H H L Z H L L H H H L counter divider delayed LOW to HIGH edge delayed HIGH to LOW edge transient pulse suppression frequency recognition digital pulse duration selector
Programmable 8-bit counter (1) INPUTS ACTIVE LOW A B C D E F G H Note 1. All inputs A to H HIGH is not allowed. 1 2 4 8 16 32 64 128 VALUE
12-bit predivider W L L H H X L H L H CLOCK FOR PROGRAMMABLE COUNTER CP/X X=1 X =16 X = 256 X = 4096
January 1995
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Philips Semiconductors
Product specification
Universal timer module
FUNCTIONAL DESCRIPTION Clock divider and decoder The clock signal at input CP is, at its original frequency, the system clock, but it also drives the programmable counter. The counter input frequency can be predivided by the factors 1/16, 1/256 and 1/4096, depending on the logic state of inputs W and X (according to the function tables above). 8-bit programmable counter The 8 inputs A to H are the set inputs of the 8 counter flip-flops. The setting is triggered by an edge of the input signal (at input IN) depending on of the chosen mode. Event flip-flops, synchronization and edge-detection The event flip-flops are used to recognize the positive and/or negative edge of the input signal at IN. Parts of the flip-flops are used together with the programmable 8-bit counter as a retriggerable mono-flop, which defines the time scaling for event recognition. The input IN is synchronized by the clock signal CP.
HEF4753B LSI
Mode switch and output multiplexer This function switches the chosen output to the output (OUT) and gives the mode of which the edge at input IN has to be detected. The inputs Z, Y and LFC give 7 modes +1, that means in mode `Digital Filter' the input LFC can be HIGH or LOW. OPERATING MODES The circuit has 6 operating modes which are activated by the logic state of inputs LFC, Y and Z. An extra mode is possible by using two circuits which are connected such so they function as a digital band-filter. 1. Counter mode (LFC = LOW; Y = LOW; Z = HIGH) In this mode the output OUT should be connected to input IN. If not, only one counter cycle starts after a transition at input IN (see Fig.3 and note 1.).
A H
B H
C L
D H
E H
F H
G H
H H
W L
X L
LFC L
Y L
Z H
Fig.3
Timing diagram for counter mode; t1 = delay until set of 8-bit counter; t2 = delay to set 8-bit counter; t3 = predefined delay by programming.
January 1995
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Philips Semiconductors
Product specification
Universal timer module
2. Divider mode (LFC = LOW; Y = HIGH; Z = LOW)
HEF4753B LSI
In this mode the output OUT should be connected to input IN. If not, only one counter cycle starts after a transition at input IN (see Fig.4 and note 1.).
A L
B L
C H
D H
E H
F H
G H
H H
W L
X L
LFC L
Y H
Z L
Fig.4 Timing diagram for divider mode; t1 = delay until set of 8-bit counter; t2, t3 see Fig.3.
3. Delayed LOW to HIGH edge mode; see note 2. (LFC = HIGH; Y = HIGH; Z = LOW)
A H
B L
C H
D H
E H
F H
G H
H H
W L
X L
LFC H
Y H
Z L
Fig.5
Timing diagram for delayed LOW to HIGH edge mode; t1 = delay until set of 8-bit counter; t2 = delay to set 8-bit counter; t3 = predefined delay by programming; t4 = delay until next negative clock edge; t5 = delay until next positive clock edge.
January 1995
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Philips Semiconductors
Product specification
Universal timer module
4. Delayed HIGH to LOW edge mode; see note 2. (LFC = HIGH; Y = LOW; Z = HIGH)
HEF4753B LSI
A H
B L
C H
D H
E H
F H
G H
H H
W L
X L
LFC H
Y L
Z H
Fig.6 Timing diagram for delayed HIGH to LOW edge mode; for t1 to t5 see Fig.5.
5. Transient pulse suppression and pulse delaying mode; see note 2. (LFC = Y = Z = HIGH) In this mode the circuit is working as a digital low-pass filter. An undisturbed pulse will only be delayed (see Fig.7).
A L
B L
C H
D H
E H
F H
G H
H H
W L
X L
LFC H
Y H
Z H
Fig.7 Timing diagram for transient pulse suppression and pulse delaying mode; for t1, t2 and t3 see Fig.5.
January 1995
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Philips Semiconductors
Product specification
Universal timer module
6. Frequency recognition mode (LFC = LOW; Y = HIGH; Z = HIGH)
HEF4753B LSI
The incoming signal must be symmetrical within the limits as given by the specified delay time in note 2., to achieve lower or higher frequency detection (see Fig.8).
A L
B H
C L
D H
E H
F H
G H
H H
W L
X L
LFC L
Y H
Z H
Minimum dividing number is 3.
Fig.8
Timing diagram for frequency recognition mode; tx = time shorter than t3 (OUT = H); ty = time greater than t3 (OUT = L); for t1, t2 and t3 see Fig.5.
January 1995
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Philips Semiconductors
Product specification
Universal timer module
7. Digital pulse duration selector mode (Y = Z = LOW)
HEF4753B LSI
This mode is a combination of two circuits, both used for frequency recognition. Both circuits are driven by the same clock and same input signal, but programmed for different frequencies. The LFC input of the low-frequency circuit is set to logic LOW, the output is connected to the LFC input of the high-frequency circuit, whose output (OUT) is the `filter' output. The delay time depends on the same facts as given in note 2.. For timing diagram see Fig.9.
A L L
B L L
C L H
D H H
E H H
F H H
G H H
H H H
W L L
X L L
LFC L OUT (IC1)
Y H L
Z H L IC1 IC2
Minimum dividing number is 3.
Fig.9
Timing diagram for digital pulse duration selector mode; tIN1, tIN2 and tIN3 are the IN input pulse durations; t1 = predefined delay by programming IC1; t2 = predefined delay by programming IC2.
Notes to operating modes 1. The number of clocks for one cycle in the counter and divider mode is: a. Contents of programmable counter plus one if X = W = LOW. b. Contents of programmable counter multiplied by 16, 256 or 4096 if X and/or W = HIGH. 2. The delay in the modes 3, 4, 6 and 7, and the delay which is identical to the maximum duration of the transient pulse in mode 5 depend on the optional divided clock frequency, the input conditions of the 8-bit presetable counter and in addition, different times of propagation delays, jitter and maximum one half of a clock frequency period. January 1995 8
Philips Semiconductors
Product specification
Universal timer module
HEF4753B LSI
DC CHARACTERISTICS VSS = 0 V Tamb (C) VDD V Output (sink) current LOW (pin 10) Output (source) current HIGH (pin 10) 4,75 10 15 5 10 15 4,6 9,5 13,5 -IOH VOH V VOL V 0,4 0,5 1,5 IOL SYMBOL -40 - - - - - - + 25 - - - - - - + 85 - - - - - -
MIN. MAX. MIN. 2,7 9,5 24,0 0,6 1,8 6,0 2,3 8,0 20,0 0,5 1,5 5,0
MAX. MIN. MAX. 1,8 6,3 16,0 0,4 1,2 4,0 mA mA mA mA mA mA
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP OUT HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH Input rise and fall times pins 13, 14, 17 Maximum clock pulse frequency pins 17; = 50% 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax 3 7 8 6 14 17 MHz MHz MHz tr, tf no limit tTLH tTHL tPLH tPHL SYMBOL MIN. TYP. 420 180 120 450 200 140 30 15 10 60 30 20 MAX. 850 360 250 900 400 280 60 30 20 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns TYPICAL EXTRAPOLATION FORMULA
January 1995
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Philips Semiconductors
Product specification
Universal timer module
HEF4753B LSI
VDD V Dynamic power dissipation per package (P) 5 10 15
TYPICAL FORMULA FOR P (W) 1 800 fi + (foCL) x VDD2 8 000 fi + (foCL) x VDD 19 000 fi + (foCL) x VDD
2 2
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
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